With the scaling of integrated circuits, applications require an increasingly faster speed. This puts a requirement on the metal-oxide-semiconductor (MOS) devices, demanding that the MOS devices switch faster. As is known in the art, to increase the speed of MOS devices, high dielectric constant values (k values) of the gate dielectrics are desired. Since conventional silicon oxide, which has a k value of about 3.9, cannot satisfy such a requirement, high-k dielectric materials, which include oxides, nitrides, and oxynitrides, are increasingly used.
High-k dielectric materials, however, have high trap densities, and thus cannot be used close to the channel regions of the MOS devices. A stacked gate dielectric scheme has been introduced to accommodate the benefit of the high-k materials and conventional oxides that have low trap densities. Typically, a base oxide layer is formed on the channel region, followed by the formation of a high-k material on the base oxide layer. The stacked layers function as a gate dielectric layer.
A shortcoming with the existing stacked gate dielectric layer is the reduction of effective oxide thickness (EOT). In a conventional base oxide formation process, diluted HF is used for removing native oxide on the surface of the semiconductor substrate. Standard clean processes, which typically include a standard clean process 1 and a standard clean process 2, can also be used for cleaning the surface of the substrate. A native oxide may then be formed on the clean surface of the substrate. Using this method, the thickness of the base oxide layer can be lowered to between about 9 Å and about 10 Å. The effective oxide thickness (EOT) of the stacked layer, which includes the EOT of the base oxide layer and about 30 Å of a high-k dielectric layer, may be lowered to about 14 Å and about 15 Å accordingly. Further lowering of the EOT of the gate dielectric, however, has been limited, mainly due to the thickness of the base oxide layer. This is because although reducing the thickness of the base oxide layer can cause the reduction of the EOT, as is commonly perceived, further reduction of the thickness of the base oxide is not feasible. One of the reasons is that the surface condition of the traditionally formed oxides is thickness dependent, and the surface condition affects the quality of the subsequently formed high-k film. A base oxide layer typically needs to have a certain thickness in order to have a substantially smooth surface.
Accordingly, what is needed in the art is a MOS device that may incorporate a stacked gate dielectric layer to take advantage of the benefits associated with both a high-k dielectric and a base oxide layer while at the same time overcoming the deficiencies of the prior art.